An arithmetic processing device such as a processor having pipelines divides each of instructions into multiple stages, and then causes the pipelines to execute the respective instructions. Such an arithmetic processing device includes, for example, an instruction decode unit configured to decode an instruction, arithmetic units each configured to execute an inputted instruction, and reservation stations configured to issue the decoded instructions to the arithmetic units (see Japanese Laid-open Patent Publication Nos. 2000-105699 and 2011-8732). The reservation station holds instructions supplied from the decode unit and sequentially inputs the instructions, that become executable, among the held instructions to the arithmetic units. Since the order of instructions to be executed by the arithmetic units is changed by the reservation stations, the efficiency of executing the instructions is made better than in a case where no reservation stations are used.
In addition, when an execution result of a first instruction is used in a second instruction that follows the first instruction, the execution result of the first instruction may bypass a register, and be inputted to the arithmetic unit as input of the second instruction before being stored into the register. In this case, the efficiency of processing instructions is made better than that of the processing without such bypassing.
For example, in a case where a first instruction is inputted to the arithmetic unit, the reservation station detects whether any of instructions held in the reservation stations has a register dependency on the first instruction, and thereby detects a second instruction that will use the execution result of the first instruction. Then, if detecting the second instruction, the reservation station inputs the second instruction to the arithmetic unit and in a cycle next to a cycle where the second instruction is detected. In this next cycle, if the execution result of the first instruction is inputted to the arithmetic unit while bypassing the register, the processing of the second instruction may be completed rapidly.
In addition, when the reservation station detects dependencies of all the instructions held in the reservation stations on the first instruction, time to detect the dependencies between the first instruction and the other instructions also increases as the number of instructions held in the reservation stations increases. Therefore, when the number of instructions held in the reservation stations increases, the detection of dependencies between instructions may not end within the cycle in which the first instruction is inputted to the arithmetic unit. In this case, the second instruction is not inputted to the arithmetic unit in the cycle next to the cycle in which the first instruction is inputted to the arithmetic unit, and accordingly the efficiency of processing the instructions is lower than that in a case where the second instruction is inputted to the arithmetic unit in the cycle next to the cycle in which the first instruction is inputted to the arithmetic unit.
In one aspect, the arithmetic processing device and the processing method of the arithmetic processing device of the present disclosure aim to suppress a decrease in the efficiency of processing instructions even when the number of instructions held in the reservation stations increases.